TSMC is exploring panel-level packaging and is working on its CoPoS technology, but the company’s Kevin Zhang says wafer-level packaging technologies is considerably more advanced than panel-level packaging.
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Fashion brands struggle to adopt new technologies despite constant innovation. PDS and Future Fashion Assembly aim to bridge the gap between solutions and implementation.
TSMC is executing the largest manufacturing expansion in semiconductor industry history that combines simultaneous multi-fab N2 ramps, AI-driven manufacturing optimizations, and massive CoWoS/SoIC packaging capacity expans…
More robots equals more jobs? That’s the pitch from a robot-making company that just raised $200 million at a $1 billion valuation.
Humanoid robots are impressive, but companies should judge them by economics, reliability, and cost per task, not by how human they look.
Chinese startup Prinano claims it produced 8-inch photonic chip wafers without DUV lithography, using nanoimprint technology that cuts costs by 90%.
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TSMC says it does not have enough capacity to handle all the demand from AI hyperscalers, with CEO C.C. Wei saying that it will take a long time before it can match customer demand. This is an opportunity for Intel, thoug…
Samsung displayed its first physical mockup of HBM5 memory at Computex 2026 in Taipei, pairing the eighth-generation AI memory with a new in-package cooling structure.
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South Korean media has noted a surge in spending on luxury goods following big bonus payouts to semiconductor workers.
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If you’re from Pittsburgh, you may want to sit down for this one: global EV sales leader BYD claims the aluminum frame that underpins its new Yangwang U8L SUV passes a brutal, 12 ton lift test – despite weighing over 100 lbs. less than a comparable ste…