IBM goes sub-1nm, develops 0.7nm-class technology — offering up to 50% higher performance and 70% higher energy efficiency compared to IBM’s 2nm-class node
 IBM goes sub-1nm, develops 0.7nm-class technology — offering up to 50% higher performance and 70% higher energy efficiency compared to IBM’s 2nm-class node

IBM’s new 0.7nm-class fabrication process uses nanostack transistors, requires 2x more FEOL steps for massive improvements in performance, power, and area.

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TSMC is reportedly hiking prices for ‘all advanced nodes,’ accounting for 74% of the company’s wafer business — Nvidia, AMD, Apple, Qualcomm, and others will face higher wafer costs

TSMC has reportedly told customers to prepare for 5% to 10% price hikes across advanced chip nodes, extending beyond 3nm to include 7nm and some legacy processes.

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Humanoid Livestream: Robot Makers Rushing To Show Machines On Real Production Lines

I see your dancing robot and raise you a robot that can do actual work, live, while being streamed. Humanoid makers are getting real …

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Rare ASML Special Edition Monopoly board unearthed in social media trade — enthusiast swaps 2007 employee gift for High-NA EUV Lego kit

We just witnessed a significant semiconductor industry related non-cash trade deal take place on Twitter/X.

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ASML denies US government report that its EUV chipmaking tool was shipped to China — says ‘rumors’ are ‘inaccurate and damaging to our reputation’

U.S. Commerce Secretary Lutnick expresses concerns in a conversation with ASML executives that China has an EUV lithography system as ASML denies shipping such scanners to the PRC.
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Post-silicon era gets closer as industry giants crack the 2D transistor scaling bottleneck with breakthrough tech — imec, ASML, and TSMC fab complementary 2D-material transistors at 50nm pitch on a 300mm wafer

Imec, ASML, and TSMC have integrated both n-type and p-type transistors with atomically thin 2D channels on a single 300mm wafer.
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Intel’s fab roadmap examined — Arizona, Ohio, Ireland, and the two deadlines deciding 14A process node

This roadmap provides an in-depth analysis of Intel’s current plans for its chip production capacity.

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No, NYT, It’s Not ‘Nearly Impossible’ To Build Robots Without China

The NYT recently said it’s almost impossible to build robots without China. There are counter-examples very close to home, however …

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Intel’s performance-enhanced 18A-P process enters risk production — drop-in 18A upgrade promises 9% performance improvement at iso-power, cuts thermal resistance by 40%

Intel’s enhanced 18A-P has entered risk production, laying the groundwork to ramp the node into full production in the coming months.
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Chinese fab SMIC’s 7nm metal pitch beats Intel 18A but lags 38% on density, teardown finds — Huawei’s sanctions-beating HiSilicon Kirin 9030 is the first subject of SemiAnalysis’s new teardown lab

SemiAnalysis has published the first teardown from its new in-house lab, focusing on the minimum local metal pitch on SMIC’s third-gen 7nm at 32.5nm.
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